Field
The disclosure relates generally to a voltage regulator and, more particularly, to output current monitoring circuit thereof.
Description of the Related Art
Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor process variation, and temperature is key to many applications. Additionally, power consumption is also a key design requirement.
In a recent power management integrated circuit (PMIC), precise output monitoring of a buck is required for more efficient power management of processors. Average output current is sensed and digitized, and used for controlling processors.
FIG. 1 shows average output current monitor in a circuit known to the inventor. The buck 100 is composed of pulse width modulation (PWM) controller 105 and output stage 130. Output current monitor is sampling timing generator 170, sampler and sense circuit 150. The PWM controller 105 has an input signal from Master clock output signal 102, and Error amplifier 115. The Error amplifier 115 a vout signal 120 and reference signal vref 125. The PWM controller 105 generates two output signals pdrv 111 and ndrv 112. The Output stage 130 contains p-channel metal oxide semiconductor (PMOS) 135 and pre-drive inverter 140, and re-channel metal oxide semiconductor (NMOS 145). The Output stage 130 drives node LX 136 which is connected to inductor 152, capacitor load C 153, and Load 154 for the output voltage level vout 155. The sample timing generator 170 receives a signal from ndrv 112. The sample timing generator 170 contains an AND logic gate 175 and delay device 180. The output of the Sampling timing generator 170 is connected to the Sense 150 to generate an Output current information 160.
FIG. 2 shows the timing diagram 200 for the signals. The master clock PWM controller 105 of FIG. 1 generates PWM signals, pdrv 220 and ndrv 230. Pdrv is activated with master clock rising 210. Pulse width of pdrv is determined by the control signal from the error amplifier. When pdrv 220 is deactivated, ndrv 230 is activated immediately and keeps active until master clock rising 210.
Output stage 130 is composed of PMOS 135 and NMOS 145. PMOS is turned on when pdrv is active and NMOS is turned on when ndrv is active. The output, LX node 136 swings almost rail-to-rail and the inductor current swing in triangular waveform. The voltage drop is caused by the inductor current. The voltage drop during NMOS is turned on is expressed as Rnon*I(LX) using NMOS on-resistance Rnon.
FIG. 2 highlights ndrv delay signal ndrv_dly 240, sample signal nsample 250, and current and voltage of the LX node 136, I (LX) 260, and V (LX) 270. Current monitor circuit is composed of sampling timing generator 170 and sense circuit 150 of FIG. 1. The sense circuit 150 estimates the average output current information 160 from the average of the voltage drop across the NMOS during sampling signal, nsample 250 of FIG. 2 is activated.
Sampling timing generator generates nsample 250 from NMOS on signal, ndrv. The sampling generator of prior art is composed of delay Td1 and AND logic. To wait LX node 136 voltage settling, start of nsample 250 is delayed from ndrv while end of nsample is almost the same as ndrv. So the center of sampling timing is shifted by Td1/2 from the center of NMOS on-timing, and it causes sensing error. Using the delay Td1 180 in the sampling timing generator 170, the sensing error is expressed as:ΔIsense=dILX/dt*Td1/2=−Vout/L*Td1/2It is affected by on the output voltage Vout and inductance L.
U.S. Patent Application 20100033146 to Irissou et al., describes a method for providing output (e.g., current) sensing and feedback in switching power converter topologies. Some embodiments include feedback functionality for generating a converter driver signal (for driving the switching converter) and/or a sample driver signal (for driving the sampling module) as a function of sensed output feedback from the sampling module
U.S. Patent Application 20080316781 to Liu, describes a buck converter LED driver circuit is provided. The driver circa, includes a buck power stage, a rectified AC voltage source, a voltage waveform sampler, and a control circuit.
U.S. Pat. No. 6,894,464 to Zhang, describes a multi-phase synchronous buck converter having plural single phase synchronous buck converter stages, connected together to provide an output current to a load. A sensing circuit in each converter stage includes a variable gain current sense amplifier.
U.S. Pat. No. 6,803,750 to Zhang, describes a device constructed of a plurality of single phase buck converter stages, and a sensing circuit for each converter stage to generate an output signal representative of the output current provided by that converter stage.
WO 1999031790 to Clark et al, describes a regulator with a sampling circuit that makes measurements of an electrical characteristic of the voltage regulator at discrete moments of time. A feedback circuit is coupled to the sampling circuit and the switch, and is configured to use the measurements to control the duty cycle to maintain the DC voltage substantially constant.
In these prior art embodiments, the solution to establish a sampling circuit in switching regulator utilized various alternative solutions.